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Altera_Forum
Honored Contributor
13 years agoclocked video output underflow and display flickers
Hi I'm doing a qsys design which is composed of a sdi rx, a clocked video input, a deinterlacer, an interlacer, a clocked video output, and a sdi tx. This design simply receives an interlace...
Altera_Forum
Honored Contributor
13 years agoYour SDI reception clock is too inaccurate, so You must use GenLock for SDI RX to recover the SDI clock properly. Check SiLabs.