Honored Contributor
Honored ContributorHello,
@Gareth Duncan: You cave me somekind of hint when you said there was a lost_sync problem. Indeed there is, the 3th bit of the status Register (VCO) is constantly giving a five as output, which means the buffer is underflowing (I think). I already changed the "start FIFO output" of the VCO to about 2/3ths (600/800) of the original FIFO size, instead of 0, which didn't change a thing yet. I also have some good news, I found in my collection of examples an example design for the NEEK(!) which uses (almost) every feature of the VIP suite. I cannot upload it immediatly for you because the zip file is about 125 MB (I will put it on rapidshare as fast as I can, so you can all download it and experiment with it). The name of the design is NEEK_VIP_demo_LCD_SVGA_v91_r1_src, I don't find the original zip file back and I don't know where I downloaded it (it must be a long time ago) @Peet: I already added the SOPC file to the post here and as you can see, they also use the frame buffer between the alpha blender and the VCO. May be this is necessairy to output a nice stream of data. (just a thought) A second thought goes to the use of his own verilog programmed "serializer" for the video output streams. All the components in the SOPC use a 3 pixel in parallel transmission (which is not good for the NEEK VGA and LCD) and after the VCO he added some verliog code to serialize those three pixel data blocks for transmission to the MAX II on the LCD board. Could there be a problem with the serial data stream we used? I have to run now, I'm sorry I cannot upload the example immediately, I will do it as fast as I can, because I think you'll all be interested! But I think for now there is some light at the end of the tunnel! I will start this example design from scratch and study every possibility next week to understand the real flow of the VIP. Have a nice weekend! Best, Hans
