Clocked Video Output behavior

I am using MicroTronix's Multi-channel DDR2 controller with frame buffer. Its settings are bit different from Altera's one.

For the frame buffer, I am using 1920x1080 input/output frame resolution, 8 bits per pixel and 3 parallel frames. The sync setting are default for DVI 1080pMy input video is at 148.5 MHz (1080p60) but I am using 160 MHz clock for all the Altera VIP cores to cater for delays in packet processing. I used a PLL on my Stratix-III FPGA to provide me 160MHZ VIP_CLK from reference clock of 50 MHZ. There is another PLL which generates clocks for the DDR2 memory, it is 267MHz.

I have 64 DQ lines connected to DDR2, so for frame buffer I set 128 bit bus width, 512 entries pixel buffer and 128/256 burst size (both work ok). Also I am using tripple buffering, that is, enabled frame drop and repeat.

I hope now you know all the settings that I am using for frame buffer.