Forum Discussion

marqs_ic's avatar
marqs_ic
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Clocked Video Input II vid_datavalid width is 1 regardless of pixels in parallel parameter

Hi, I'm feeding oversampled video into CVI II IP and trying to make it only read every Nth pixel. There seems to be vid_datavalid signal for exactly this purpose, but its width does not get expand...
  • ZH_Intel's avatar
    ZH_Intel
    3 years ago

    Hi marqs_ic,

    Good day.

    Thank you for your input.

    Will convey it to our internal team on this.

    Do you still have further inquiries on this issue?

    If there is no further question, I will transition this thread to community support.

    Thank you.

    Best Regards,

    ZulsyafiqH_Intel

marqs_ic's avatar
marqs_ic
Icon for New Contributor rankNew Contributor
3 years ago

Hi,

I'm not sure why simulation would be needed to confirm the issue. Just instantiating CVI II IP in Platform Designer (configured with at least 2 pixel in parallel) and generating verilog shows that vid_datavalid input port width is always 1. The overall design is not based on any examples or reference design.