Forum Discussion

marqs_ic's avatar
marqs_ic
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Clocked Video Input II vid_datavalid width is 1 regardless of pixels in parallel parameter

Hi, I'm feeding oversampled video into CVI II IP and trying to make it only read every Nth pixel. There seems to be vid_datavalid signal for exactly this purpose, but its width does not get expand...
  • ZH_Intel's avatar
    ZH_Intel
    3 years ago

    Hi marqs_ic,

    Good day.

    Thank you for your input.

    Will convey it to our internal team on this.

    Do you still have further inquiries on this issue?

    If there is no further question, I will transition this thread to community support.

    Thank you.

    Best Regards,

    ZulsyafiqH_Intel

marqs_ic's avatar
marqs_ic
Icon for New Contributor rankNew Contributor
3 years ago

I've checked the width of vid_datavalid from top-level verilog generated by Platform Designer, and its width is 1 while e.g. vid_de width matches VIP 'pixels in parallel' (2 in my case):

input  wire [1:0]   alt_vip_cl_cvi_0_clocked_video_vid_de,
input  wire         alt_vip_cl_cvi_0_clocked_video_vid_datavalid,