Clocked Video Input II vid_datavalid width is 1 regardless of pixels in parallel parameter

Sorry for late reply. As an answer to your earlier question, the video fed into CVI II IP is oversampled as said in the first post, thus tieing vid_datavalid high is not a solution.

A simple example would be video oversampled by 3, i.e. every 3rd pixel needs to be marked as valid so that only those will be processed downstream. If the video pipeline runs e.g. 2 pixels in parallel, then I'd assume vid_datavalid width should be 2 as well so that each pixel fed into the pipeline via CVI II can be individually set as valid or invalid.

Now that vid_datavalid is a single bit regardless of pixels in parallel, it's only possible to set a group of 2 consecutive pixels as valid or invalid. My workaround thus is a FIFO where only valid pixels are stored and which reads 2 pixels per clock if there are enough stored in the FIFO.

It would be good if the feature was fixed or at least its current limitations would be documented.