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Altera_Forum
Honored Contributor
Honored ContributorChaining DMA PCIe Reference Design freezes when Cpl with a "non-successful" Status
The Chaining DMA PCIe Reference Design does not handle Completions with a "non-successful status". For example, I had accidentally set the Host Address to read from the wrong place in my MRd R...
Altera_ForumHonored Contributor
Honored ContributorJust saw that in the Verilog version of the CDMA reference design, the 2nd bug i mentioned (tx_desc_fmt_64) has been resolved. The VHDL version is converted from the Verilog version (using XHDL I think) and I must not have the most updated version.
Is there a up to date VHDL version of the CDMA reference design?
