Forum Discussion
Altera_Forum
Honored Contributor
13 years agohave solved the problem. it was due to the .do file generated by quartus.
transcript on
if {} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vcom -93 -work work {D:/WyBaby/Documents/SIEMENS/FPGA/Project/9_2frame_1/src/tse_mac.vho}
vcom -93 -work work {D:/WyBaby/Documents/SIEMENS/FPGA/Project/9_2frame_1/src/tse_mac.vhd}
vlog -vlog01compat -work work +incdir+D:/WyBaby/Documents/SIEMENS/FPGA/Project/9_2frame_1/src/triple_speed_ethernet-library {D:/WyBaby/Documents/SIEMENS/FPGA/Project/9_2frame_1/src/triple_speed_ethernet-library/altera_tse_reset_synchronizer.v}
vcom -93 -work work {D:/WyBaby/Documents/SIEMENS/FPGA/Project/9_2frame_1/simulation/modelsim/tse_mac_tb.vhd}
vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive -L rtl_work -L work -voptargs="+acc" tse_mac_vhd_tst
add wave *
view structure
view signals
run 100 us
i changed the position of line 8 and line 9 and 'do run_msim_rtl_vhdl.do', then it gave the right output. then what is the .vho file and how does it work? thx a lot in advance.