PDone
Occasional Contributor
Occasional ContributorCannot Simulate FIR II in VHDL
I used both Quartus 18.1 and 20.1 to create a FIR II IP in VHDL. Most of the files created are VHDL, but there is one file, altera_avalon_sc_fifo.v that is Verilog. I am simulating with Active HDL 1...
Hi,
Glad to hear that it is working. For your information, the Modelsim Intel FPGA Starter Edition has lower performance than Modelsim Intel FPGA Edition which requires license. You can also use Modelsim SE for better performance.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
