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Altera_Forum's avatar
Altera_Forum
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12 years ago

Cannot resolve algebric loop

Developed a simulink model by importing VHDL design of FIR compiler II IP. I integrated a vhdl wrapper (to buffer the input data based on sink_valid and sink_ready) import to feed the input to the fi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Your design in Simulink contains a loop with no delays. (At least no delays Simulink can see since it can't actually see into your HDL Import block).

Presumably you've connected the sink_ready output to some logic which then drives sink_valid and sink_data. You could resolve this by inserting a delay block on your ready path. The specifics of doing that may be quite tricky but should be possible.