Can PCIe IP compiler be used with external Phy?

Hi Wincent,

MDIO is a serial interface used to communicate with an Ethernet PHY. I'm trying to interface with a PCI express PHY which is a totally different thing.

PCI express (or PCIe) is a high speed (1.5 Gbit/sec) serial bus that's primarily used by add-on cards in PCs. It's the communication channel that the add-on card uses to communicate with the PC it's installed in.

Some Intel FPGAs with high speed transceivers include a hard IP core for PCIe built in. I'd love to use one of those, but I've had 3000+ Cyclone IV GX parts on order for over a year and have not received any. I'm now getting desperate and trying to redesign my product to use a Cyclone V E part which I do have in stock. That part doesn't support the high speed transceivers, so I'll need to use an external PHY chip.

PCIe PHY chips, such as the TI part I mentioned (XIO1100) use a standard interface to convert a parallel bus to the high speed PCIe serial bus. This interface is called PIPE (PHY Interface for PCI Express). When using such a chip the FPGA still handles the upper level PCIe protocol in a soft IP core and communicates with the PHY chip which handles the high speed serial interface.

The IP compiler for PCIe that Altera provides used to support using an external PCIe PHY chip. I have attached an old version of the user's guide for that IP. Chapter 14 is all about using an external PHY with that IP. The current PCIe IP included with Quartus and Qsys only appears to support parts with high speed transceivers and PCIe hard IP. That IP doesn't help me because the part I'm using doesn't include that hardware.

Is the more compete version of the IP compiler for PCIe still available?

Thank you,

Steve