BER Degradation Observed When Enabling Multiple DFE-Adapted Channels on Arria 10 GX

Hi Onur,

Based on your observations, it appears that the issue may be related to a potential noise-coupling or signal-integrity effect when a larger number of channels are operating with DFE adaptation enabled. Please find my responses to your questions below.
1. What could be causing this degradation when the number of DFE-adapted channels is increased? Are we exceeding some power, thermal, or resource limitation? Could there be an interaction between DFE-enabled channels in adjacent banks or through the shared clocking/power distribution networks?
[CP] To help narrow down the root cause, I would recommend monitoring the device power rails when the issue occurs and verifying that all supplies remain within the recommended operating specifications.

2. Could this issue be attributed to silicon-level crosstalk between the DFE-adapted channels? More specifically, is it possible that enabling a larger number of DFE-adapted transceivers introduces additional noise coupling or interference within the FPGA silicon, potentially degrading the signal integrity of adjacent or nearby channels? If so, what would be the recommended approach to isolate or mitigate such effects in our current design and test environment?
[CP] Could you please provide more details regarding how DFE adaptation is being used in your design? For example:

Is the DFE adaptation process being triggered manually?
If so, at what point in the system operation is the adaptation initiated?

Regarding the possibility of crosstalk, one potential source may be the board-level signal environment rather than the FPGA silicon itself. To help isolate the issue, I would recommend removing the external serial loopback connection and enabling the internal serial loopback feature. If the issue no longer occurs with internal loopback enabled, this would suggest that external signal-integrity factors may be contributing to the observed behavior. This test can help distinguish between board-level effects and issues originating within the device itself.

3. Is there a known limitation on the number of transceivers that can reliably support a 10 Gbps data rate simultaneously across a wide temperature range?
[CP] I am not aware of any documented limitation that restricts the number of transceivers operating at 10 Gbps under the conditions you described.
At this stage, I would recommend performing the power-supply monitoring described in Question 1, as well as the internal serial loopback test suggested in Question 2. The results from these experiments should help further narrow down the potential root cause and determine whether the issue is related to power integrity, board-level signal integrity, or another factor.

Please keep me updated on your findings, and I will be happy to review the results and assist with the next steps.

Thank you.