AVMM address mapping

For AVMM master (we have rename this as host) port:

When you mentioned that you set BAR0 Size = 256MB for the PCIe end point configuration, this means the PCIe endpoint exposes 256MB of addressable space to the host system.

The host can perform reads/writes within this range.

With the AVMM Master Port Address Width = 28 bits, this allows the AVMM master to generate addresses from 0x00000000 to 0x0FFFFFFF, which is exactly 256MB of addressable space. [2^28 = 268,435,456 bytes = 256 MB] So the address space matches the BAR0 size.

With Data Width = 512 bits (64 bytes) , each AVMM transaction can transfer 64 bytes of data at once. However, this does not multiply the address space—it just increases the bandwidth per transaction. 64 bits Byte Enable allows fine-grained control over which bytes in the 64-byte data word are valid during a read/write.

For AVMM slave (agent) port:

Address Signal Width = 10 bits (2^10 =1024) This means the AVMM agent can decode 1024 addresses.

Data width = 64 bits (8 bytes) Each address points to a 64-bit word, not a single byte. So1024 * 8 bytes = 8192 bytes (~ 8Kb)

With 8 bits Byte Enable, this allows selective access to individual bytes within the 64-bit word.

For further details on the Avalon® -MM Agent Addressing, you may checkout this user guide:

https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/mm-agent-addressing.html

Additionally, Platform Designer supports auto base address assignment for Avalon® -MM components. In the Address Map tab, click Auto Assign Base Address.

Regards,

Richard Tan