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K606's avatar
K606
Icon for Contributor rankContributor
5 months ago
Solved

Avalon Streaming Dual Clock FIFO

Hi, I am trying to connect the AV DC FIFO as followed: The idea being that the main clock is running at 100MHz and is connected to the mSGDMA which reads from the FIFO, and iopll is outputtin...
Pcie
  • ShengN_altera's avatar
    ShengN_altera
    4 months ago

    Hi,


    Understood that. Could you try to use the simple adapter ST handshake clock crosser under the bridges and adapters section? I think you're connecting it correctly previously. Instead of using dual clock fifo under on-chip memory section, as it's embedded peripheral I'm not sure is there anything needs to take note when using it.


    Regarding why booting slow when using 200mhz, you need to open a new thread target pcie to get the related pcie expert helps.


    Thanks,

    Regards,

    Sheng




ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
5 months ago

Hi,


I just realised you use st dual clock fifo ip already, that ip will handle cdc already.

Not sure is that the lock reset problem of the pll, could you signal tap the pll to the osillator?

Also try replace that iopll with another clock source does the problem resolved?


Thanks,

Regards,

Sheng


K606's avatar
K606
Icon for Contributor rankContributor
5 months ago

The issue is that during boot I cannot actually load the initial design onto the fpga, and so cannot use signal tap!