Forum Discussion
ContributorAvalon Streaming Dual Clock FIFO
Hi,
Understood that. Could you try to use the simple adapter ST handshake clock crosser under the bridges and adapters section? I think you're connecting it correctly previously. Instead of using dual clock fifo under on-chip memory section, as it's embedded peripheral I'm not sure is there anything needs to take note when using it.
Regarding why booting slow when using 200mhz, you need to open a new thread target pcie to get the related pcie expert helps.
Thanks,
Regards,
Sheng
Super ContributorHi,
I just realised you use st dual clock fifo ip already, that ip will handle cdc already.
Not sure is that the lock reset problem of the pll, could you signal tap the pll to the osillator?
Also try replace that iopll with another clock source does the problem resolved?
Thanks,
Regards,
Sheng
K606The issue is that during boot I cannot actually load the initial design onto the fpga, and so cannot use signal tap!
