Forum Discussion
ContributorAvalon Streaming Dual Clock FIFO
Hi,
Understood that. Could you try to use the simple adapter ST handshake clock crosser under the bridges and adapters section? I think you're connecting it correctly previously. Instead of using dual clock fifo under on-chip memory section, as it's embedded peripheral I'm not sure is there anything needs to take note when using it.
Regarding why booting slow when using 200mhz, you need to open a new thread target pcie to get the related pcie expert helps.
Thanks,
Regards,
Sheng
Super ContributorHi,
Seems like a cdc problem where msgdma read from fifo at 100mhz but oscillator write to fifo at 200mhz.
If you make the clock frequency same does the problem resolved? If yes, I would suggest you to add one Avalon® -ST Streaming Pipeline Stage IP in between the msgdma and fifo reading to increase the reading frequency to 200mhz
Thanks,
Regards,
Sheng
K606Many thanks for the reply!
Could you tell me, is this the only Avalon® -ST Streaming Pipeline Stage IP Docs?
In fact, if the design you suggest is this one:
Am I correct? If so would I be correct to say that if this IP would be placed in between the oscillator and the FIFO, then the read speed would stay at 100 MHz?
Many thanks!
