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Altera_Forum's avatar
Altera_Forum
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13 years ago

Avalon ST to FFT megafunction variable speed

Hi everyone, I have an implemenation of the FFT megacore, currently under the Avalon ST interface In front of this I have a fifo the data coming in to the system is relatively slow, possib...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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clock gating isn't really safe in FPGAs. It is better to use the valid signal and deassert it when you don't have any new data to give to the Avalon sink.

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Ok, thanks,

so deasserting Valid mid packet doesnt do any harm though?

Thanks again