Avalon-ST Ready signal held low

Hi Piyush,

Good Day.

Firstly before I suggest a configuration, based on (MIPI IP <---> Avalon-ST FIFO <--> V):

May I know how is the frame buffer II IP connection? Position of the frame buffer? A simple diagram of your design would help.

In order to use Frame buffer IP ,it is required to follow the Intel® Video and Image Processing (VIP) Suite User Guide. It is not necessary to use Avalon-ST FIFO when using VIP suite, instead the FIFO function is already embedded in VIP suite IP functions. For example in Frame buffer IP, it already have FIFO function embedded in the IP.

For VIP design, it is required to have Clocked Video Input II IP block first in order to convert clocked video formats to Avalon streaming video, before Frame buffer IP block.

Thank you.

Best Regards,

ZulsyafiqH_Intel