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Altera_Forum
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10 years ago

Avalon ST custom IP component

Hello, I'm having trouble creating my own component that uses Avalon Streaming Interface in QSys. Based on the VIP demonstartion for DE1-SoC I want to have a connection between the Altera VIP F...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Korn,

Thank you for this helpful reply.

Yes, I'm inserting pixel-processing components into a video pipeline. The new components must respect the VIP streaming protocol so that they'll interoperate correctly with VIP suite cores.

One way or another, we're required to implement a state machine to keep track of what just came in on din_data.

Indeed, checking the low-order nibble when SOP is asserted, as you suggest, is essential.

I'm wrestling with a simplest such state machine. Since every single IP core to be connected to a VIP suite core requires this logic, I'm surprised that there is no example in the VIP Suite User Guide or on the forum. Maybe I'm just missing it?