Avalon-ST backpressure with SGDMA

I received this answer back from Altera:

"Although the SG-DMA changes the status of valid signal after it receives the valid ready signal, it doesn’t impact the design of sink. Because sink can set its ready signal according its own status, and it samples the stream data when valid and ready assert in the same cycle. There is no necessary to wait the valid signal in order to output the ready signal."

In other words, the SGDMA violates the Avalon-ST specification of zero-ready-latency devices, by not asserting valid until the sink asserts ready, but Altera is not going to fix it. I've asked that they at least update the Avalon-ST and/or SGDMA documentation.

So, I was curious if their Avalon-ST Multiplexer would work with SGDMA? Well, it does. Looking at the generated verilog below for an 8:1 mux, they take the source valid signal and invert it to create the ready signal back to that source. So the ready signal for all inputs is asserted even though they're really not ready. This allows the SGDMA to assert valid, which it then holds until the mux sink is really ready.

   // ---------------------------------------------------------------------
   //| Back Pressure
   // ---------------------------------------------------------------------
   always @* begin
      in0_ready <= ~in0_valid	;
      in1_ready <= ~in1_valid	;
      in2_ready <= ~in2_valid	;
      in3_ready <= ~in3_valid	;
      in4_ready <= ~in4_valid	;
      in5_ready <= ~in5_valid	;
      in6_ready <= ~in6_valid	;
      in7_ready <= ~in7_valid	;
      case(select) 
         0 : in0_ready <= selected_ready;
         1 : in1_ready <= selected_ready;
         2 : in2_ready <= selected_ready;
         3 : in3_ready <= selected_ready;
         4 : in4_ready <= selected_ready;
         5 : in5_ready <= selected_ready;
         6 : in6_ready <= selected_ready;
         7 : in7_ready <= selected_ready;
         default : in0_ready <= selected_ready;
      endcase
   end