Forum Discussion
New ContributorAvalon MM Clock Crossing Bridge - Handshake not an option?
That may be true if your Avalon interconnect is entirely within a QSYS subsystem. However, this is apparently not the case when the IP core is used stand-alone: in QSYS export all the ports of the IP, generate, and then instance the resulting IP as a module in your custom HDL. The simulation and implementation appear to work *only* in the pipelined read with variable latency mode, when used outside of the QSYS ecosystem. I have verified this in signaltap as well as in simulation.
Super ContributorHi,
Check this document https://www.intel.com/content/www/us/en/docs/programmable/683609/23-1/faq.html (page 207):
The clock crossing bridge contains a pair of clock crossing FIFOs, which isolate the host and agent interfaces in separate, asynchronous clock domains. When you use a FIFO clock crossing bridge for the clock domain crossing, you add data buffering. Buffering allows pipelined read hosts to post multiple reads to the bridge, even if the agents downstream from the bridge do not support pipelined transfers.
Thanks,
Best Regards,
Sheng
bhuntThat may be true if your Avalon interconnect is entirely within a QSYS subsystem. However, this is apparently not the case when the IP core is used stand-alone: in QSYS export all the ports of the IP, generate, and then instance the resulting IP as a module in your custom HDL. The simulation and implementation appear to work *only* in the pipelined read with variable latency mode, when used outside of the QSYS ecosystem. I have verified this in signaltap as well as in simulation.
