avalon mm byte enable

Yes that is the case. So if you wanted to perform a 16 bit access to addresses 2-3 of your slave port the master would present an address of 0 with byte enables 1100. By the time the access hits the slave port it'll be presented as a 16-bit bit word offset of 1 and both byte enables will be high. Also this assumes the master presents byte address and the slave accepts word addresses. Qsys now lets you specify word/byte accessor for both masters and slaves, I typically stick to SOPCB style addressing (masters=byte, slave=word) so that my stuff will work in both tools.

At the end of the day if you have a master and slave that follows the Avalon specification you don't really need to care what the interconnect does. That's the whole point of having the spec.

In your .tcl code if you tell it to perform a 16-bit access at say address 2 then the master will figure out what to present to the fabric for you (address = 0, byte enable = 1100). You just need to make sure that the address you perform reads and writes to are aligned to the width of the access you are performing.