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Altera_Forum
Honored Contributor
11 years agoavalon MM burst read command and waitrequest
Hi all, I'm realizing a custom Avalon MM Slave, which should be able to operate in burst mode. Focusing on burst READ commands, I have a doubt about the possibility that a single master asks fo...
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- Yes. Your interface state machine can assert waitrequest at the end of the clock period where you accept the read transaction, and keep it asserted until the last data phase of readdatavalid assertion. I just posted a tutorial on using the Avalon-MM Master BFM which include VHDL source code. Take a look at it. There is a burst example in the Modelsim simulation. http://www.alteraforum.com/forum/showthread.php?t=48928 Use the BFM to test your component. My test example does not generate lots of different Avalon-MM sequences, but the example will be enough to get you started. Cheers, Dave --- Quote End --- Thank you!! It works! I'll look at your tutorial for sure. Thanks again :)