avalon MM burst read command and waitrequest

--- Quote Start ---

Yes.

Your interface state machine can assert waitrequest at the end of the clock period where you accept the read transaction, and keep it asserted until the last data phase of readdatavalid assertion.

I just posted a tutorial on using the Avalon-MM Master BFM which include VHDL source code. Take a look at it. There is a burst example in the Modelsim simulation.

http://www.alteraforum.com/forum/showthread.php?t=48928

Use the BFM to test your component. My test example does not generate lots of different Avalon-MM sequences, but the example will be enough to get you started.

Cheers,

Dave

--- Quote End ---

Thank you!!

It works!

I'll look at your tutorial for sure.

Thanks again :)