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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Avalon - Wishbone Interface

Well, I get that IP-Module from opencores.org: http://opencores.org/?do=project&who=a_vhdl_can_controller

So far so good. My problem is, that this IP uses a Wishbone Interface and I need an Avalon Interface.

I tried to do convert it with comb. logic(can_top_vhdl.vhd) but it doesnt work. The old top level entity was can_top.v. Can somebody tell me what I am doing wrong?

PS: I get a warning in the SOPC-Builder:

"byteenable[4] width must be one eighth of data width(8)" I dont have any glue why I get this warning. I got a Nios II CPU with 32 Bits and my byteenable signal is 4 Bits wide.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    You are better off looking at www.niosforum.com. I believe that there is an avalon version of this core already. If not, there are walk throughs. wishbone and avalon are very similar.

    --dalon
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    from your file can_top_vhdl

    your data port is 8 bit wide to avalon, so no need for byteenable.

    if you add a 4 bit byteenable then your data port is 32bit wide.

    byteenable[3] is data[31:24]

    byteenable[2] is data[23:16]

    byteenable[1]is data[15:8]

    byteenable[0] is data[7:0]

    so you have 2 possabilities

    remove byteenable

    extend data port
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Well thx, I found some finished core(avalon) on niosforums.

    It also doesnt work without byteenable. I just know now, that the wishbone interface is very bad documented.