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Rk_Athram's avatar
Rk_Athram
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4 years ago

ATX PLL in the DisplayPort IP generated design example

Hi, I have gone through the UG :Intel® Arria® 10 DisplayPort IP Core Design Example User Guide UG-20075, and example design https://fpgacloud.intel.com/devstore/platform/17.0.0/Standard/arria-1...
Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hi,

These registers are available in FPLL section, and these are used for storing link rate and load back the link rate,

can these registers will work for ATX PLL too ?