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Rk_Athram's avatar
Rk_Athram
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4 years ago

ATX PLL in the DisplayPort IP generated design example

Hi, I have gone through the UG :Intel® Arria® 10 DisplayPort IP Core Design Example User Guide UG-20075, and example design https://fpgacloud.intel.com/devstore/platform/17.0.0/Standard/arria-1...
Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

In display port design for FPLL is used, which having registers to store the frequency band, the similar registers are not available for ATX PLL.

SNAPSHOT FROM A10 register map excel sheet.

I need to figure out whether i can use the existing logic from display port for switching speed when i use ATX PLL without re calibrating after changing speed?