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ADufl's avatar
ADufl
Icon for New Contributor rankNew Contributor
5 years ago

Associate an individual mif file to each RAM memory instantiated by a "generate"

Hello, I instantiate RAM memories with the following VHDL code : gen_inst_ram_0to7 : for i in 0 to 7 generate inst_ram : ram port map( address_a => w_address_a(i), address_b => w_address_b...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

You can try to study the RAM VHDL design code in Quartus. In the new VHDL file, right-click and "insert template". Find VHDL > Full Designs > RAMs and ROMs > Single-Port RAM with Initial Contents.

There is a part of the design code on how to use .mif file. Or you can instantiate it using the Quartus IP Catalog. Hope it helps.