Arria V Hard IP for PCI Express Root-point issue

Is this a board, you are designing now, or is it already done?

The third option is to use the SOC variation of the Cyclone V, and use one of the ARM cpu's to control the PCIe.

Out of the three, this is probably the quickest to get up and running, and the simplest for your software engineers to understand (ARM CPU's are well understood).

NIOS would be my second choice, in most case. Both both the ARM and NIOS subsystems you need to get familiar with QSYS and build your SOC up via that program.

You can use logic to do the sending/requesting, but unless you need absolute minimum overhead/latency in your system, this is much more difficult to implement.

Take a look at the SOC's I've used the Cyclone V variation, and Zynq variation (Xilinx) and have been impressed. Altera's QSYS is a better tool for connecting the components and IP.

The number of LE's available in the SOC's are less, but remember, you will not be using ANY LE's or memory blocks for the processor blocks. (Hardcores), where to get a high performance NIOS, will take significant resources.

Regards

Pete