Forum Discussion
New ContributorARRIA V GZ PCIe Equalization
Hi Tom,
I did note a comment about enablign AEQ during Phase 2, I think we have this enabled in Quartus project but not sure if this is only being enabled durign Phase 2. Will check this at our end.
Can you confirm that this needs to be enabled/disabled programatically, and only during stage 2?
E.g. it should not be on before Stage 2?
>>I never encounter this question before , but I just answer to you based on my own understanding, please correct me if you feel I am wrong. During the Equalization phase (Phase 2), the AEQ feature is used to adjust the equalization settings of the PCIe transceivers in real-time based on the quality of the received signal. This helps to ensure a stable and reliable data transfer link.
The AEQ feature can be enabled or disabled programmatically in your firmware project using the appropriate registers provided by the PHY IP Core. It is recommended to enable the AEQ feature only during Phase 2 of the PCIe link training process and disable it before Phase 2 to avoid any interference with the link training process.
Let me know if you have different thoughts.
Regards,Wincent_Intel
Regular ContributorHi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Regards,
Wincent_Intel
TomLithgowHello Wincent,
Yes, I think we have the answer that we had been looking for.
The EQ parameters and Controls are part of the Tranciever Reconfiguration Controller registers, not in the PCIe block, which makes sense. We can read the EQ results as per the registers mentioned here;
Also noted that below it is stated that the transcievers can be manually read/written as explained here;
Thank you for the assistance.
Regards,
Tom Lithgow
