Forum Discussion
New ContributorARRIA V GZ PCIe Equalization
Hi Tom,
I did note a comment about enablign AEQ during Phase 2, I think we have this enabled in Quartus project but not sure if this is only being enabled durign Phase 2. Will check this at our end.
Can you confirm that this needs to be enabled/disabled programatically, and only during stage 2?
E.g. it should not be on before Stage 2?
>>I never encounter this question before , but I just answer to you based on my own understanding, please correct me if you feel I am wrong. During the Equalization phase (Phase 2), the AEQ feature is used to adjust the equalization settings of the PCIe transceivers in real-time based on the quality of the received signal. This helps to ensure a stable and reliable data transfer link.
The AEQ feature can be enabled or disabled programmatically in your firmware project using the appropriate registers provided by the PHY IP Core. It is recommended to enable the AEQ feature only during Phase 2 of the PCIe link training process and disable it before Phase 2 to avoid any interference with the link training process.
Let me know if you have different thoughts.
Regards,Wincent_Intel
Regular ContributorHi Tom,
To check the link equalization, you may refer to
But it is for gen3 data rate for PIPE mode.
Hope this able to help you.
Regards,
Wincent_Intel
TomLithgowHello Wincent,
Thank you for the link, and this information.I have reviewed this section before and it is quite infromative about the processes required and what is and isn't supported.
It does not really give very much detail about how this should/can be achieved.
I did note a comment about enablign AEQ during Phase 2, I think we have this enabled in Quartus project but not sure if this is only being enabled durign Phase 2. Will check this at our end.
Can you confirm that this needs to be enabled/disabled programatically, and only during stage 2?
E.g. it should not be on before Stage 2?
Also I noted the comment about the AEQ Registers, I believe that this is the detail that we have been looking for:
equalization results
This is the value set by the automatic AEQ adaptation performed at startup. If you choose to perform manual equalization using the linear equalizer, you can use this value as a reference. Although automatic and manual equalization do not provide identical functionality, specifying this value enables manual equalization to approximate the original setting.
Regards,
Tom Lithgow
- Wincent_Altera
Hi Tom,
I did note a comment about enablign AEQ during Phase 2, I think we have this enabled in Quartus project but not sure if this is only being enabled durign Phase 2. Will check this at our end.
Can you confirm that this needs to be enabled/disabled programatically, and only during stage 2?
E.g. it should not be on before Stage 2?
>>I never encounter this question before , but I just answer to you based on my own understanding, please correct me if you feel I am wrong. During the Equalization phase (Phase 2), the AEQ feature is used to adjust the equalization settings of the PCIe transceivers in real-time based on the quality of the received signal. This helps to ensure a stable and reliable data transfer link.
The AEQ feature can be enabled or disabled programmatically in your firmware project using the appropriate registers provided by the PHY IP Core. It is recommended to enable the AEQ feature only during Phase 2 of the PCIe link training process and disable it before Phase 2 to avoid any interference with the link training process.
Let me know if you have different thoughts.
Regards,Wincent_Intel
