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TomLithgow's avatar
TomLithgow
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3 years ago
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ARRIA V GZ PCIe Equalization

Hello, We have a design based on the ARRIA V GZ utilising PCIe Gen3. Some questions have been raised around the specific Equalization settings being applied under various conditions, but at the ...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi Tom,

    I did note a comment about enablign AEQ during Phase 2, I think we have this enabled in Quartus project but not sure if this is only being enabled durign Phase 2. Will check this at our end.

    Can you confirm that this needs to be enabled/disabled programatically, and only during stage 2?

    E.g. it should not be on before Stage 2?

    >>I never encounter this question before , but I just answer to you based on my own understanding, please correct me if you feel I am wrong. During the Equalization phase (Phase 2), the AEQ feature is used to adjust the equalization settings of the PCIe transceivers in real-time based on the quality of the received signal. This helps to ensure a stable and reliable data transfer link.

    The AEQ feature can be enabled or disabled programmatically in your firmware project using the appropriate registers provided by the PHY IP Core. It is recommended to enable the AEQ feature only during Phase 2 of the PCIe link training process and disable it before Phase 2 to avoid any interference with the link training process.

    Let me know if you have different thoughts.

    Regards,

    Wincent_Intel

TomLithgow's avatar
TomLithgow
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3 years ago

Hello Wei Chuan,

Thank you, but not this is not the same issue.

I am aware of the PCIe limitation regarding Data Link Feature Exchange.

What we are looking for in this support thread is a way to check the applied PCIe Equalization parameters, or Preset, after our PCIe add in card is enumerated and detected and working correctly.

What is the recomended processes to read the applied Equalization Settings on the PCIe transcievers within our Firmware project?

Regards,

Tom Lithgow