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TomLithgow's avatar
TomLithgow
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3 years ago
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ARRIA V GZ PCIe Equalization

Hello, We have a design based on the ARRIA V GZ utilising PCIe Gen3. Some questions have been raised around the specific Equalization settings being applied under various conditions, but at the ...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi Tom,

    I did note a comment about enablign AEQ during Phase 2, I think we have this enabled in Quartus project but not sure if this is only being enabled durign Phase 2. Will check this at our end.

    Can you confirm that this needs to be enabled/disabled programatically, and only during stage 2?

    E.g. it should not be on before Stage 2?

    >>I never encounter this question before , but I just answer to you based on my own understanding, please correct me if you feel I am wrong. During the Equalization phase (Phase 2), the AEQ feature is used to adjust the equalization settings of the PCIe transceivers in real-time based on the quality of the received signal. This helps to ensure a stable and reliable data transfer link.

    The AEQ feature can be enabled or disabled programmatically in your firmware project using the appropriate registers provided by the PHY IP Core. It is recommended to enable the AEQ feature only during Phase 2 of the PCIe link training process and disable it before Phase 2 to avoid any interference with the link training process.

    Let me know if you have different thoughts.

    Regards,

    Wincent_Intel

TomLithgow's avatar
TomLithgow
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3 years ago

Hello Wincent,


Thank you, we just wanted to verify that the same issue did not exist for the older ARRIA V GZ device.

We are working to confirm if the Equalization settings are correctly being applied to the PCIe link, when we read the PCI config space via the host we see values that seem to always be default:

11:8 - Upstream Port 8.0GT/s Transmitter Preset (HwInit)
This field holds the Transmit Preset value sent or received during 8.0GT/s Link Equalization.
- 0000b      =      De-emphasis = -6dB; Preshoot = 0dB

and

14:12 - Upstream Port 8.0GT/s Receiver Preset Hint (HwInit)
This field holds the Receiver Preset Hint value sent or received during 8.0GT/s Link Equalization.
- 000b      =      -6dB

This has raised some concern as to whether the Equalization settings negotiated is in fact being applied.

Regards,

Tom

  • TomLithgow's avatar
    TomLithgow
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello Wincent,

    Just to add to the above, a specific question;

    • How can we know if Link training has occurred correctly i.e. that the PCIe Physical layer EQ in the transceivers has been set up correctly?

    Is there a mechanism that we can use to query/confirm the Transiever set up in regard to PCIe and the EQ presets?

    Any guidance in this would be greatly appreciated.


    Tom Lithgow