Arria 2 DDR3 shared PLL

16 transmit or receive channels? At what data rate? The dedicated True LVDS silicon requires a PLL on that side(as there is a dedicated, low skew low jitter clock tree from the PLL to the SERDES). This generally doesn't combine with DDR3 since they use a top/bottom PLL. That being said, many applications don't need "True LVDS" and work fine with just a PLL. If you're pushing the limits, say 1GB data rates, you need True LVDS, but otherwise might be all right with the LVDS I/O standard, the I/O's double-data rate registers, and a global clock(driven from a PLL elsewhere in the chip).