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TomCarpenter's avatar
TomCarpenter
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Arria 10 Transciever Toolkit - Custom PRBS Verifier

Hi, We are trying to use the Transceiver Toolkit to verify a JESD204b link to work out the best receiver parameters for our link. Unfortunately the ADC we are using is not capable of outputting a r...
Jesd
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,

User custom pattern can be sent through the tx_parallel_data port only. The NPDME adds the JTAG master interface only so that user can easily connect to internal register space via system console.


Regards


TomCarpenter's avatar
TomCarpenter
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

I could be misunderstanding something, but I'm not sure how that helps me.

I don't have any of the transmitter lanes broken out on the board, and simply looping back within the transceiver lane in the FPGA surely doesn't help me test the BER of an incoming receive lane.

Or are you saying that the transceiver can directly compare the incoming data on the RX lane from outside the FPGA with that of the transmit lane (as it it were a loopback external to the FPGA)?