Forum Discussion
lcy2000
New Contributor
New ContributorArria 10 PCIe Gen 3 stuck at Equalization.Phase3
Hi, I'm writing a design with Arria 10 AVST PCIe IP (Quartus 24.3). Currently we have encountered equalization problem at PCIe Gen3. We are using A10GX1150 DevKit as an add-in card attached to a...
Hi ChenYang,
In my understanding of PCIe, contrary to MalfTLP, BadTLP is a much more underlayered concept with a only a few reasons to trigger: (1) Link CRC error (2) Sequence Number error. (Refer to PCIe 3.0 Spec, Figure 3-17, Page 185/860)
>> Okay
>> Another that that you could check will be- Do you check if your endpoint has received the 8 required consecutive TS2's ?
- But before it is able to complete sending 16 TS2s, the downstream port sends EIEOS and then starts sending TS1 ?
- Based on my experience, once it meet sending 16 TS2, it shall transition to Recovery.idle since the requirement for that transition are meet >>Recovery.equilization phase X >> L0.
Regards,
Wincent_Altera
Wincent_Altera
Regular Contributor
Regular ContributorHi,
As we do not receive any response from you on previous question/reply/answer that we provided. Please login to “https://supporttickets.intel.com/s/?language=en_US’, view details of desire request, and post a feed/response within net 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on follow-up questions.
Regards,
Wincent_Altera
