Forum Discussion
New ContributorArria 10 PCIe Gen 3 stuck at Equalization.Phase3
Hi ChenYang,
In my understanding of PCIe, contrary to MalfTLP, BadTLP is a much more underlayered concept with a only a few reasons to trigger: (1) Link CRC error (2) Sequence Number error. (Refer to PCIe 3.0 Spec, Figure 3-17, Page 185/860)
>> Okay
>> Another that that you could check will be- Do you check if your endpoint has received the 8 required consecutive TS2's ?
- But before it is able to complete sending 16 TS2s, the downstream port sends EIEOS and then starts sending TS1 ?
- Based on my experience, once it meet sending 16 TS2, it shall transition to Recovery.idle since the requirement for that transition are meet >>Recovery.equilization phase X >> L0.
Regards,
Wincent_Altera
Regular ContributorHi,
May I know which driver that you are using ? is it driver provided in the Example design itself ?
Please check your BIOS setting, ensure that it is set as "gen3" according to your design instead of "AUTO".
See if this able to solve your problem or not
Else.
But after loading the driver, I saw ltssmstate of the IP drops to Equalization.Phase3 and never come back.
>> Recovery.Equalization with Phases 0–3, reflects progress through Gen3 equalization. Phases 2 and 3 of link equalization are optional. Each link must progress through all four phases, even if no adjustments occur. If you skip Phases 2 and 3, you speed up link training at the expense of link BER optimization
>> if the BER optimization is not something you needed you may ignore it
>> For detailed information about the four-stage link equalization procedure for 8.0 GT/s data rate, refer to Section 4.2.3 in the PCI Express Base Specification, Rev 3.0.
>> Seen Phase 3 is optional process, and in your design it not pass through, you may consider to skip it to enable your project feature.
Hope this clarified,
Regards,
Wincent_Altera
