Forum Discussion
Aflop
Occasional Contributor
Occasional ContributorArria 10 PCIe DMA Bus Mastering
Background: I have been working with the Arria 10 GX Devkit and using the PCIe with DMA HIP. I have the general scheme working with 5 BARs of memory with a few minor kinks. Problem : In addition ...
RongY_altera
Contributor
ContributorIf no further questions, I'll transit this case to community support. Thanks.
AflopOccasional Contributor
Occasional ContributorI have looked at the AN-829 Documentation for the DMA Example, downloaded the associated template file, and examined the project. It is not quite what I am looking for. All DMA transactions for this example are initiated by the host PC and the FPGA design is passive. I need DMA transactions to be initiated by the FPGA. The Host PC will do the initial act of reserving a memory block, then telling me the 64bit address. The FPGA will then send data when it is available. It is not a Host-to-FPGA read action initiated by the Host. It is a FPGA-to-Host write action done when the FPGA is ready. Are there examples of this or can a procedure be provided?
