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Aflop's avatar
Aflop
Icon for Occasional Contributor rankOccasional Contributor
8 months ago

Arria 10 PCIe DMA Bus Mastering

Background: I have been working with the Arria 10 GX Devkit and using the PCIe with DMA HIP. I have the general scheme working with 5 BARs of memory with a few minor kinks. Problem : In addition ...
Pcie
RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
7 months ago

The DMA example implements such data transfer. You may check the interrupt function in the driver.


Generally a Host PC is based on an OS so an interrupt handle has to be registered with an IRQ first (done by a driver). Once FPGA raises an interrupt, the Host will receive it and feedback to FPGA a transaction completion, then FPGA unmasks the interrupt.


Regards,

Rong