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fpga_user1's avatar
fpga_user1
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2 months ago

Arria 10 Native PHY 66:64 RX wrong word with valid asserted

I am using Arria 10 Native PHY in Basic Enhanced PCS mode at 12.5 Gbps for a custom protocol. The protocol layer is implemented in FPGA fabric. The Native PHY is intended to provide the serial trans...
Transceiver
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
1 month ago

Hi,

 

Thank you for the update.

 

It appears that I am unable to locate the other case in our internal system at the moment. Let me check with the forum moderators and see if they can help identify the related case.

 

In the meantime, to facilitate the debugging process and ensure that we have a common understanding of the issue, could you please share a simulation example along with the detailed steps required to reproduce the observed behavior?  This information will help us investigate the issue more effectively while we work on locating the other case.

 

Please let us know if you have any concerns or questions.

 

Thank you.

fpga_user1's avatar
fpga_user1
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1 month ago

Hi,
Thanks for your reply.

With regards to another case: don't worry about it, this post is the actual case I want to discuss. I did two attempts to publish my question but the system was tagging it as spam.

Regarding the simulation of the issue: I cannot upload the full design, but for this case, as my data is scrambled prior to enter the XCVR, it would be the same if a PRBS is used. In that case it should report the same symptoms: the data from XCVR is flagged as valid but the actual received data is not correct.

Thanks.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hi,

     

    Thank you for the update.

     

    Just to check check if you are able to create a simple test design (for example, using a fixed data pattern or an incremental data pattern) that can reliably reproduce the observed behavior? Having a simple reproducible design would help us replicate the issue on our side and facilitate the debugging process by using a known and controlled data pattern.

     

    If possible, please upload the design files to the support case. If the files are too large or cannot be attached to the case, you may also try sending them directly to me at [email protected].

     

    Thank you for your assistance, and I look forward to your feedback.

    • fpga_user1's avatar
      fpga_user1
      Icon for New Contributor rankNew Contributor
      1 month ago

      Hi,
      Thanks for your reply.

      I'm not sure I'll have time to create a specific design. But to reproduce the issue, it should be as simple as using a PRBS connected to the XCVR, I was wondering if you may have internal reference designs to test the IPs so maybe we could reuse one?
      In the mean time I'm assuming that the rx valid signal always asserted to 1 is not true and there is no possible way to achieve what I initially wanted. I.e. the data will not valid be valid every ~33 clocks.

      Thanks.