Arria 10 DDR4 EMIF Burst Length Expansion

That is for allowing different component interfaces to communicate with each other in the generated system interconnect. It does not change the capabilities of the actual IP that communicates with the RAM outside the system. So your master interface could issue a 512 burst to the memory controller (the slave). The adaptor translates this into a burst size that works for the IP and the IP issues commands to the external RAM. Responses back to the master would be translated as well. It depends on if this is the behavior you want.

Note also that the burst adaptor on its own adds a large amount of logic to the design and can often be the cause of timing issues in the system, which are ugly and difficult to debug since it's inside the generated interconnect. The handbook text you mention is indicating to add bridges, which would get placed on either side of the burst adaptor to help minimize the burst adaptor logic.