Arria 10 DDR4 EMIF Burst Length Expansion

Isn't one of the purposes of the QSYS interconnect logic to generate fifos and adapter logic to manage the different widths and burst capabilities of interfaces?

From the quartus handbook (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii5v1.pdf), p.8-16:

using bridges to minimize adapter logic

Qsys generates adapter logic for clock crossing, width adaptation, and burst support when there is a

mismatch between the clock domains, widths, or bursting capabilities of the master and slave interface

pairs.

Qsys creates burst adapters when the maximum burst length of the master is greater than the master burst

length of the slave. The adapter logic creates extra logic resources, which can be substantial when your

system contains master interfaces connected to many components that do not share the same characteris‐

tics. By placing bridges in your design, you can reduce the amount of adapter logic that Qsys generates.

This tells me that adding an Avalon-MM Pipeline Bridge with my desired max burst size will implicitly add all the required burst size adaptations. Should I be wary of this assumption?

Thanks,

Andrew