Forum Discussion
Occasional ContributorArria 10 - PCIe Hard IP - 2x PCIe Gen3x8 OR 1xPCIe Gen3x16
Hi Aflop,
"1 IP for the first 8 channels and another IP for the next 8 channels"
I think it depends on whether the 16 channels (RX and TX signals) in the FPGA are from the same bank.
1. If they are from the same bank, you can only instantiate 1 PCIe IP even though the next 8 channels (in the case of Gen3 x8) are unused. This results in 1 PCIe device.
2. If they are from the same bank, you can instantiate 1 PCIe IP and perform PCIe bifurcation Gen3 2x8, allowing it to work as two separate PCIe devices. However, this requires the PCIe IP to support PCIe bifurcation. In your case, unfortunately, Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express does not have support to PCIe bifurcation. https://www.intel.com/content/www/us/en/docs/programmable/683647/18-0/features.html
3. On the other hand, if they are from a separate bank, and you instantiate 2 Gen3 x8 PCIe IP, I think the one endpoint hardware can be recognized and enumerated by the host as two separate PCIe endpoint devices.
Thanks.
Best Regards,
Ven
Frequent ContributorHi Aflop,
My apologies for the delayed response.
Yes, Arria® 10 or Cyclone® 10 GX PCIe IP does support AVMM DMA Gen3 x8.
However, instantiating two Gen3 x8 PCIe IP blocks does not create a Gen3 x16. Instead, the two Gen3 x8 PCIe IPs are treated as two separate Gen3 x8 PCIe endpoint devices by the host, and they will have separate BARs. Additionally, they are enumerated by the host as two distinct PCIe endpoint devices, meaning they will not be combined into a single Gen3 x16 PCIe endpoint device.
I hope this addresses your inquiries.
Thanks.
Best Regards,
Ven
