anyway to improve the reliability of triple SDI rx IP

Hi rbugalho

The SDI receiver IP is from Altera so I don't know how the clock recovering is implemented in detail.

I just know its functions and IO signals.

I am now trying to solve all the negative slack.

Luckily, I solve most timing violations by adding asynchronous clock groups.

(My design has other clocks for audio data and other modules which are not related to the video clock.)

Hope I can solve the rest timing violations.

Thank you for your help.