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Altera_Forum
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13 years ago

anyway to improve the reliability of triple SDI rx IP

Hi My design has a triple SDI transceiver and several video processing IPs. A basic test for this design is to use video standards of SDI (487i, 576i, 720p, 1080i, and 1080p) as input and to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi rbugalho

The SDI receiver IP is from Altera so I don't know how the clock recovering is implemented in detail.

I just know its functions and IO signals.

I am now trying to solve all the negative slack.

Luckily, I solve most timing violations by adding asynchronous clock groups.

(My design has other clocks for audio data and other modules which are not related to the video clock.)

Hope I can solve the rest timing violations.

Thank you for your help.