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Altera_Forum's avatar
Altera_Forum
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13 years ago

anyway to improve the reliability of triple SDI rx IP

Hi My design has a triple SDI transceiver and several video processing IPs. A basic test for this design is to use video standards of SDI (487i, 576i, 720p, 1080i, and 1080p) as input and to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi,

I'm not familar with SDI. Maybe you can describe it and your receiver a bit more?

Meanwhile, some general suggestions:

1) Setting constrains and fixing the negative slacks is *the* way. Working without *correct* constraints is working without safety net.

2) Using LogicLock is not an alternative to setting constrains (nothing is) but may be a way to fix negative slacks.

3) Clock groups and false paths are used to simply remove paths from analysis. This should only be used when the paths are indeed asynchronous (and hence not possible to analyse) and you are using asynchronous design techniques. Otherwise, you're just sweeping issues under the carpet.