anyway to improve the reliability of triple SDI rx IP

Hi,

I'm not familar with SDI. Maybe you can describe it and your receiver a bit more?

Meanwhile, some general suggestions:

1) Setting constrains and fixing the negative slacks is *the* way. Working without *correct* constraints is working without safety net.

2) Using LogicLock is not an alternative to setting constrains (nothing is) but may be a way to fix negative slacks.

3) Clock groups and false paths are used to simply remove paths from analysis. This should only be used when the paths are indeed asynchronous (and hence not possible to analyse) and you are using asynchronous design techniques. Otherwise, you're just sweeping issues under the carpet.