Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

AN690 (S5 PCIe reference design) Testbench Support

Hello, . I apologize if this has been asked and answered already, but I'm having trouble generating BFMs for this reference design: . http://www.altera.com/support/refdesigns/ip/interface/re...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The SV HIP Status Output Bridge doesn't has a simulation model, it is neccessary to disable this component in Qsys before generate the testbench.