Forum Discussion
AqidAyman_Altera
Regular Contributor
2 years agoHello,
Thank you for reaching out Intel FPGA Community.
Based on the snapshot you shared, it shows a syntax error which means the issue is in the line or statement in the code which does not conform with the Verilog syntax rules. I would recommend you check first on any possible syntax error in the code or upgrading the Verilog version to the latest one and see if the issue is resolved.
Regards,
Aqid