Altsyncram mixed port width issue

ssterll, you right, I've noticed that the table is for Arria 10 afterwards. But it is not the main point. And, by the way, Cyclone V Handbook refers back to ug_ram_rom.pdf. I.e. in "Mixed-Width Port Configuration" section it states the following

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embedded memory (ram: 1-port, ram:2-port, rom: 1-port, and rom: 2-port) user guide (http://www.altera.com/literature/ug/ug_ram_rom.pdf) Provides more information about dual-port mixed width support.

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There is also a table "M10K Block Mixed-Width Configurations in True Dual-Port Mode", which sort provides the answer, but not quite. It only gives the ratios for 1-32 (40) bit wide buses (just for individual M10 block, not abstract "memory"), whereas I am interested in 64-256 bit wide buses. One would suggest, that wider buses are implemented by dividing into smaller chunks, best suitable for multiple M10K blocks.

I should also point out, that the memory is instantiated as a part of QSys system. I.e. the picture with parameters in the original message is for "On-Chip Memory (RAM or ROM)" component, used as a part of QSys system. Here the combination of PortA Width=64, PortB Width=256 is valid. But, if I try to use IP-Megafunction (outside of QSys) "Onchip Memory: RAM: 2 port)", it doesn't even allow buses wider than 128-bits!

So I still have the following questions:

1) What are the possible combinations for CycloneV mixed-port memories in general? And specifically, for PortA=64, PortB=256 combination, is it a valid one?

2) Whatever the answer to the 1'st question, QSys allows to use (invalid?) parameters for onchip memory, which lead to errors during compilation (Analysis & Elaboration stage).