Altmemphy

Hello,

basically, double data rate signals aren't accessible to SignalTap. They only exist at the DDR2 I/O pin interface. You need an oscilloscope or fast logic analysator to check DDR2 timing and data content.

You say, you can't "read correctly data from DDR2SDRAM" after "resynchronisation". I assume, this is neither the case before PLL reconfig? The point is, that DDR2 calibration requires complex interaction between your controller and ALTMEMPHY. It depends particularly on your controller's ability to write and read test data when required. I think this isn't an easy design problem and can fail in many ways. I preferred using the Altera HP DDR2 controller IP.

However, if you decide to build your own controller, which could be necessary to meet particular design requirements, then simulation gives you insights to internal signal flow and DDR2 interface without fast test equipment. But due to the complex design, also simulation isn't done in a moment, it's hard work.

Regards,

Frank