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Occasional Contributoraltlvds_rx
How to make sure data is aligned with fclk when using altlvds_rx ip?
Hi,
Please refer the ALTLVDS user guide section 1.3.2: https://www.intel.com/content/www/us/en/docs/programmable/683062/17-1/lvds-serdes-transmitter-receiver-ip-36681.html
In external PLL mode rx_coreclock can be used in the fabric logic to further process the data. In this mode, rx_coreclock is same as the rx_syncclock which is an input to the ALTLVDS_RX.
rx_syncclock is used to receive the parallel data.
Regards
5 Replies
Ash_R_AlteraRegular Contributor
Hi,
Can you please tell which device IP are you using?
Regards
XQSHENEP4CE22U14A7N
- Ash_R_Altera
Hi,
The ALTLVDS IP has rx_coreclock signal. You can connect the fabric clock to it.
Regards
- XQSHEN
where is this signal, rx_coreclock ?
- Ash_R_Altera
Hi,
Please refer the ALTLVDS user guide section 1.3.2: https://www.intel.com/content/www/us/en/docs/programmable/683062/17-1/lvds-serdes-transmitter-receiver-ip-36681.html
In external PLL mode rx_coreclock can be used in the fabric logic to further process the data. In this mode, rx_coreclock is same as the rx_syncclock which is an input to the ALTLVDS_RX.
rx_syncclock is used to receive the parallel data.
Regards
