Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

ALTLVDS IP: Can serdes channels be placed into different IO banks?

Hello! I'm using cycloneV and trying to place ALTLVDS IP channels into different banks. Both TX and RX IPs are used with external PLL and channels placed into a single bank works fine, but if i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

so you see the problem.

There are no paths between clock and data pins which met the requirements you gave it with constraining the pin-locations.

It's really hard to get your problem correct. If you would post some more detail about it (maybe a block-diagram or some code with PIN-Assignments)?!